1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 ordering information part number temperature range screening level package 5962r9581801qjc -55 o c to +125 o c mil-prf-38535 level q 24 lead sbdip 5962r9581801qxc -55 o c to +125 o c mil-prf-38535 level q 24 lead ceramic flatpack 5962r9581801vjc -55 o c to +125 o c mil-prf-38535 level v 24 lead sbdip 5962r9581801vxc -55 o c to +125 o c mil-prf-38535 level v 24 lead ceramic flatpack HS1-82C12RH/sample +25 o c sample 24 lead sbdip hs9-82c12rh/sample +25 o c sample 24 lead ceramic flatpack hs-82c12rh radiation hardened 8-bit input/output port functional diagram pin description pin description di0-di7 data in do0-do7 data out ds1, ds2 device select md mode stb strobe int interrupt clr clear control and device select logic data latch and buffer (8) 2 3 int ds2 stb md ds1 service request f. f. di0-7 do0-7 clr features ? devices qml quali?ed in accordance with mil-prf-38535 ? detailed electrical and screening requirements are contained in smd# 5962-95818 and intersil qm plan - radiation hardened cmos process - total dose 1 x 10 5 rad (si) - transient upset > 1 x 10 8 rad (si)/s - latch-up immune epi-cmos > 1 x 10 12 rad (si)/s ? low power dissipation ? high noise immunity ? single power supply +5v ? low input load current ? 8-bit data register and buffer ? asynchronous register clear ? service request flip-flop for interrupt generation ? three-state outputs ? bus-compatible with hs-80c85rh cpu ? electrically equivalent to sandia sa3026 ? military temperature range -55 o c to +125 o c description the intersil hs-82c12rh is a radiation hardened 8-bit input/ output port designed for use with the hs-80c85rh radiation hardened microprocessor. it is manufactured using a self- aligned, junction-isolated epi-cmos process and features three-state output buffers and device selection and control logic. a service request ?ip-?op is included for the generation and control of interrupts to the microprocessor. the device can be used in implement many of the peripheral and input/output functions of a microcomputer system. the hs-82c12rh is pinout- and function- compatible with industry-standard 8212 devices. march 1996 spec number 518063 file number 3041.2 db na
2 hs-82c12rh pinouts 24 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t24 top view 24 lead ceramic metal seal flatpack package (flatpack) mil-std-1835 cdfp4-f24 top view 1 2 3 4 5 6 7 8 9 10 11 12 ds1 md di0 do0 di1 do1 di2 do2 di3 do3 stb gnd 16 17 18 19 20 21 22 23 24 15 14 13 vdd di7 do7 di6 do6 do5 do4 clr ds2 int di5 di4 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 1 gnd ds1 md di0 do0 di1 do1 di2 do2 di3 do3 stb vdd ds2 clr do4 di4 do5 int di7 do7 di6 di5 do6 spec number 518063
3 speci?cations hs-82c12rh absolute maximum ratings reliability information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . . gnd-0.3v to vdd+0.3v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 o c esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance q ja q jc sbdip package . . . . . . . . . . . . . . . . . . . . 55 o c/w 14 o c/w ceramic flatpack package . . . . . . . . . . . 74 o c/w 13 o c/w maximum package power dissipation at +125 o c ambient sbdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.91w ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . . . . 0.68w if device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: sbdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18.2mw/c ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . .13.5mw/c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . +4.75v to +5.25v operating temperature range . . . . . . . . . . . . . . . . -55 o c to +125 o c input low voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to +1.0v input high voltage . . . . . . . . . . . . . . . . . . . . . . . . . . vdd -1v to vdd table 1. dc electrical performance characteristics parameter symbol conditions group a subgroups temperature limits units min max high input leakage current iih vdd = 5.25v, vin = 0v, pin under test = 5.25v 1, 2, 3 -55 o c, +25 o c, +125 o c -1 m a low input leakage current iil vdd = 5.25v, vin = 5.25v, pin under test = 0v 1, 2, 3 -55 o c, +25 o c, +125 o c -1 - m a low output voltage vol vdd = 5.25v, iol = 2ma 1, 2, 3 -55 o c, +25 o c, +125 o c - 0.5 v high output voltage voh vdd = 4.75v, ioh = -2ma 1, 2, 3 -55 o c, +25 o c, +125 o c 4.25 - v static current sidd vdd = 5.25v, vin = gnd 1, 2, 3 -55 o c, +25 o c, +125 o c - 100 m a functional tests ft vdd = 4.75v and 5.25v, vih = vdd-1.0v, vil = 1.0v 7, 8a, 8b -55 o c, +25 o c, +125 o c -- - note: all devices are guaranteed at worst case limits and over radiation. table 2. ac electrical performance characteristics parameter symbol group a sub- groups temperature limits units min max data to output delay tpd 9, 10, 11 -55 o c, +25 o c, +125 o c - 105 ns write enable to output delay twe 9, 10, 11 -55 o c, +25 o c, +125 o c - 200 ns reset to output delay tr 9, 10, 11 -55 o c, +25 o c, +125 o c - 145 ns set to output delay ts 9, 10, 11 -55 o c, +25 o c, +125 o c - 100 ns clear to output delay tc 9, 10, 11 -55 o c, +25 o c, +125 o c - 135 ns output enable time te 9, 10, 11 -55 o c, +25 o c, +125 o c - 125 ns output disable time td 9, 10, 11 -55 o c, +25 o c, +125 o c - 85 ns note: 1. output timings are measured with the following conditions: cl = 100pf, vih = 3.75v, and vil = 1.0v spec number 518063
4 speci?cations hs-82c12rh table 3. electrical performance characteristics parameter symbol conditions group a subgroups temperature limits units min max input capacitance cin vdd = open, f = 1mhz, all measurements referenced to device ground t a = +25 o c-8pf output capacitance cout vdd = open, f = 1mhz, all measurements referenced to device ground t a = +25 o c-8pf pulse width tpw vdd = 4.75, vih = 3.75, vil = 1.0 9, 10, 11 -55 o c, +25 o c, +125 o c -50ns data set up time tset vdd = 4.75, vih = 3.75, vil = 1.0 9, 10, 11 -55 o c, +25 o c, +125 o c -30ns data hold time th vdd = 4.75, vih = 3.75, vil = 1.0 9, 10, 11 -55 o c, +25 o c, +125 o c -40ns note: the parameters listed in table 3 are controlled via design or process parameters and are not directly tested. these parame ters are characterized upon initial design release and upon design changes which would affect these characteristics. table 4. post 100k rad electrical performance characteristics note: the post irradiation test conditions and limits are the same as those listed in table 1 and table 2. spec number 518063
5 hs-82c12rh timing waveforms figure 1. read timing figure 2. write timing figure 3. data setup, hold, propagation delay timing figure 4. interrupt timing figure 5. clear timing ( ds, ds2) output te td 0.5vdd 0.5vdd voh vol data md or ( ds, ds2) output tpw th twe data stb or ( ds, ds2) output tset th tpd stb ( ds, ds2) int tpw tr tpw ts clr do tpw tc spec number 518063
6 hs-82c12rh functional description data latch the data latch is comprised of eight d type ?ip-?ops. the output of each ?ip-?op will follow the corresponding data input (di0 - di7) when the clock (c) is high. the clock input is level sensitive and the data becomes latched when the clock returns low. an asynchronous reset ( clr) is used to clear the latched data. since the clock (c) overrides the reset ( clr), the data must be in the latched state in order to clear the ?ip-?ops. if the data is not latched (i.e. clock is high) when clr goes low, then the q outputs of the data latch will continue to fol- low the data input, overriding the reset signal. output buffer three-state buffers are used to provide output drive for the data latch. a high level on the output buffer enable control line enables the buffer outputs. when output buffer enable is low the buffer outputs are forced to the high-impedance state. device select logic the inputs ds1 and ds2 are used for device selection. when ds1 is low and ds2 is high, the device is selected. the output buffers are enabled and the service request ?ip- ?op is asynchronously cleared when the device is selected. mode the mode input (md) is used to control the state of the output buffer and to determine the source of the data latch clock (c). when md is high, the output buffers are enabled and the source of the data latch clock (c) is the device select logic ( ds1 ds2). when md is low, the state of the output buffer is controlled by the device select logic ( ds1 ds2) and the source of the data latch clock is the strobe (stb) input. strobe the strobe input (stb) is used as the data latch clock (c) when the mode input (md) is low. the service request ?ip- ?op is synchronously set on the negative going edge of stb. service request flip-flop the service request ?ip-?op is to generate interrupts to microcomputer systems. it is negative edge triggered and asynchronously cleared (reset). the output of the service request ?ip-?op is and-gated with the device select logic ( ds1 ds2). the output of the and gate is the active low interrupt ( int) signal. spec number 518063
7 hs-82c12rh logic diagram ds1 ds2 13 device select s d q c q service request flip-flop stb 11 clr 14 md 2 latch reset di0 dq e q r 3 tsb data out enable do0 4 di1 dq e q r 5 tsb do1 6 di2 dq e q r 7 tsb do2 8 di3 dq e q r 9 tsb do3 10 di4 dq e q r 16 tsb do4 15 di5 dq e q r 18 tsb do5 17 di6 dq e q r 20 tsb do6 19 di7 dq e q r 22 tsb do7 21 int 23 latch clock spec number 518063 truth table 1. data out stb md ds1 ds2 data out equals 0 0 0 high z state 1 0 0 high z state 0 1 0 data latch 1 1 0 data latch 0 0 1 data latch 1 0 1 data in 0 1 1 data in 1 1 1 data in truth table 2. int clr ds1 ds2 stb q* int 0 reset 0001 10001 10 10 1 1 reset 0 0 0 10001 * internal service request flip-flop
8 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com hs-82c12rh metallization topology die dimensions: 90 x 76 x 14 1mils metallization: type: alsi thickness: 11k ? 2k ? glassivation: type: sio2 thickness: 8k ? 1k ? metallization mask layout hs-82c12rh (22) di7 (21) do7 (20) di6 (19) do6 (18) di5 (17) do5 (16) di4 (15) do4 do3 (10) stb (11) gnd (12) ds2 (13) clr (14) do0 (4) di1 (5) do1 (6) di2 (7) do2 (8) di3 (9) (3) di0 (2) md (1) ds1 (24) vdd (23) int spec number 518063
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